This invention relates generally to clock circuits and more particularly to phase lock loops.
Phase lock loops are widely used within clock circuits to produce a clock signal from an incoming reference signal, which may be generated by a crystal oscillator, data rate extraction circuit, etc. In addition, phase lock loops, based on scaling a feedback signal may increase or decrease the frequency of the inputted reference signal. As such, from a single clock reference, such as a crystal oscillator, a plurality of phase lock loops may be coupled thereto to produce a plurality of clock signals. Such is the case in many digital to analog and analog to digital circuits.
As is known, a phase lock loop (PLL) includes a phase detection circuit, a charge pump circuit, a voltage controlled oscillator (or current controlled oscillator), and a feedback circuit. The feedback circuit may provide a scaling factor of one, less than one, or greater than one. When the feedback scaling factor is greater than one, the output frequency of the phase lock loop will be equal to the feedback scaling factor times the frequency of the input reference signal.
In operation, a the phase detection circuit of the PLL receives the reference signal and the feedback signal and produces therefrom a phase difference signal. The phase difference signal is provided to the charge pump, which produces a charge up or charge down signal that is provided to the voltage controlled oscillator (VCO). Depending on whether the charge up or charge down signal is provided to the VCO, the VCO will adjust the frequency of the output signal accordingly. For example, if the frequency of the input signal is greater than the frequency of the feedback signal, the output frequency needs to be increased. To do this, the charge pump produces the charge up signal, which increases the input to the VCO causing the VCO to increase the output frequency. Conversely, when the output frequency needs to be decreased, i.e., due to the frequency of the feedback signal being greater than that of the input reference signal, the charge pump circuit produces the charge down signal causing the VCO to decrease the output frequency.
While phase lock loops have a wide variety of applications, their use is limited due to jitter (i.e., unwanted changes in the output frequency due to component tolerance variations). The component tolerance variation causes slight imbalances within the charge pump circuit, which cause mismatches between the steady-state charge up signal and the steady-state charge down signal. Due to the correct nature of the PLL, it attempts to regulate such imbalances, thereby producing the jitter. To reduce the effects of jitter, many phase lock loops are designed with matching transistors and use enhanced fabrication techniques. While these techniques reduce the jitter, it does not sufficiently limit it in certain applications, such as audio Codecs.
In addition to jitter, phase lock loops experience a start-up delay, during which the output frequency is varying. In a sense, the phase-lock loop is running at maximum gain until it reaches a steady state condition. The start-up delay ranges from a few hundred microseconds to a few hundred milliseconds. In many applications, including audio Codes, this delay produces undesirable results, such as noise pops.
Therefore, a need exists for a phase lock loop that has reduced jitter and/and frequency biasing to reduce start-up delays.